The present invention relates to a semiconductor integrated circuit device having a level-shifting circuit for shifting the signal amplitude.
In some semiconductor integrated circuit devices, a circuit using different voltages to input/output signals of different voltage levels is integrated in one chip. Such device incorporates a level-shifting circuit to shift, e.g., a power supply voltage level to another voltage level.
In semiconductor storage devices such as a DRAM, SRAM, and flash memory, many memory peripheral circuits use a power supply voltage to output a signal of the power supply voltage level. Of the memory peripheral circuits, e.g., a circuit for driving word lines uses a boosted voltage higher than the power supply voltage to output a signal of the boosted voltage level in order to accurately read out data of a memory cell. The level-shifting circuit shifts a signal of the power supply voltage level to a signal of the boosted voltage level.
Recently in the semiconductor storage device field, the power supply voltage is being reduced to reduce power consumption. However, the word line driving circuit must accurately read out data of a memory cell. Thus, the boosted voltage is more difficult to reduce than the power supply voltage, and the ratio of the power supply voltage to the boosted voltage is increasing. Owing to this trend, it is becoming difficult for the level-shifting circuit to output an input signal of the power supply voltage level as an output signal of the boosted voltage level.
FIG. 1A is a circuit diagram showing a conventional level-shifting circuit, and FIG. 1B is a waveform chart showing operation of this circuit.
The arrangement and operation of the level-shifting circuit will be described.
When an input signal IN101 changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level at time T1 shown in FIG. 1B, a power supply potential VCC is input to the gate of an n-channel transistor QN102 to turn on the transistor QN102. Since the transistor QN102 is turned on, the potential of a node N102 drops to turn on a p-channel transistor QP1O1. At this time, a ground potential VSS is input to the gate of an n-channel transistor QN101, so the transistor QN101 is OFF. The potential of a node N101 changes to a boosted potential VPP to change an output signal OUT101 to xe2x80x9cHxe2x80x9d level. Since the potential of the node N101 changes to the boosted potential VPP, a p-channel transistor QP102 is turned off. Then, the potential of the node N102 changes to the ground potential VSS (note that the potential of the node N102 in the circuit shown in FIG. 1A is xe2x80x9cVSSxe2x88x92VTHxe2x80x9d: VTH is the threshold voltage of the transistor QN102).
When the input signal IN101 changes from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level at time T2, the power supply potential VCC is input to the gate of the transistor QN101 to turn on the transistor QN101. Since the transistor QN101 is turned on, the potential of the node N101 drops to turn on the transistor QP102. At this time, the ground potential VSS is input to the gate of the transistor QN102, so the transistor QN102 is OFF. The potential of the node N102 changes to the boosted potential VPP. Since the potential of the node N102 changes to the boosted potential VPP, the transistor QP101 is turned off. Then, the potential of the node N101 changes to the ground potential VSS (note that the potential of the node N101 in the circuit shown in FIG. 1A is xe2x80x9cVSSxe2x88x92VTHxe2x80x9d: VTH is the threshold voltage of the transistor QN101). As a result, the output signal OUT101 changes to xe2x80x9cLxe2x80x9d level.
Note that the transistors QP101, QP102, QN101, and QN102 are of enhancement type in order to prevent a leakage current from flowing through each transistor when the input signal IN101 is at either xe2x80x9cHxe2x80x9d level or xe2x80x9cLxe2x80x9d level.
In the level-shifting circuit shown in FIG. 1A, to change the output signal OUT101 from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level as the input signal IN101 changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level, the drivability of the transistor QN102 must be set higher than that of the transistor QP102. If the drivability ratio of these transistors is small, both the transistors QN102 and QP102 stay ON, so a punch-through current flows from the boosted potential VPP to the ground potential VSS. That is, the level-shifting circuit malfunctions.
Under these circumstances, the drivabilities of the transistors QN101 and QN102 are conventionally set much higher than those of the transistors QP101 and QP102. However, a low power supply potential VCC decreases the current drivabilities of the transistors QN101 and QN102. To suppress the decrease in current drivability, the channel widths of the transistors QN101 and QN102 must be large.
To raise the switching speed, an inverter I102 for driving the transistor QN102 and an inverter I101 for driving the inverter I102 and transistor QN101 are large in size. However, this cannot avoid a long switching time Tr2 from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level and a long switching time Tf2 from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level shown in FIG. 1B, i.e., a low switching speed.
The switching speed varies more remarkably along with a decrease in power supply potential VCC. For example, the threshold voltage of a transistor varies due to manufacturing variations and the like. A low power supply potential VCC greatly influences the current amount flowing through the transistors QN101 and QN102 even with slight variations in threshold voltage. For this reason, the switching speed varies more remarkably along with a decrease in power supply potential VCC.
If the power supply potential VCC drops to values in the neighborhoods of the threshold voltages of the transistors QN101 and QN102, the level-shifting circuit shown in FIG. 1A cannot operate.
In the conventional level-shifting circuit, the switching speed decreases with a decrease in power supply voltage.
Further, if the power supply voltage drops to about the threshold voltage, the conventional level-shifting circuit cannot operate.
The present invention has been made in consideration of the above situation, and has as its object to provide a semiconductor integrated circuit device having a level-shifting circuit capable of suppressing a decrease in switching speed even if the power supply potential drops, and capable of operating even if the power supply voltage drops to about the threshold voltage.
To achieve the above object, according to the present invention, there is provided a semiconductor integrated circuit device comprising a first transistor of a first conductivity type having a source for receiving a first potential, a second transistor of the first conductivity type having a source for receiving the first potential, a gate connected to a drain of the first transistor, and a drain connected to a gate of the first transistor, and a third transistor of a second conductivity type having a drain connected to the drain of the first transistor, a gate for receiving a first signal, and a source for receiving a second signal.
In the semiconductor integrated circuit device having the above arrangement, the second signal is input to the source of the third transistor without fixing the source potential. Thus, the third transistor can be turned off by the logic level of the second signal input to the source, unlike the prior art in which the third transistor is turned off by the logic level of the first signal input to the gate. This arrangement allows operation of the semiconductor integrated circuit device even if the threshold voltage of the third transistor is set lower than in the prior art.
Assuming that a level for turning on the third transistor among the logic levels of the first signal is equal to that in the prior art, the threshold voltage of the third transistor can be decreased to increase the current amount flowing through the third transistor. Since the current amount flowing through the third transistor can be increased, deterioration of the drivability can be suppressed even if the power supply potential drops. Therefore, even if the power supply potential drops, a decrease in switching speed can be suppressed.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.